Conventional circuits are commonly formed from non-planar “fin” field effect transistors (finFETs). Conventional finFETs generally include multiple vertical fins serving as conducting channel regions. Narrowing the width of the fin channel regions improves gate control of the potential in the fin channel regions. Accordingly, conventional finFETs may be provided with narrow fin widths to reduce short-channel effects and thus enable scaling to shorter gate lengths. However, as gate lengths are scaled, conventional finFETs may fail to provide the desired performance (e.g., Ieff-Ioff). Additionally, conventional finFETs are not a gate-all-around (GAA) structure, and therefore gate control is only on sides of the fins, which limits further gate length scaling.
Future technologies have contemplated forming circuits from either gate-all-around (GAA) nanowire (NW) FETs or GAA nanosheet (NS) FETs in order to reduce short-channel effects and thereby enable scaling to shorter gate lengths. However, both GAA NW FETs and GAA NS FETs present integration problems. For instance, GAA FETs require an internal spacer to separate the GAA gate metal from the source/drain regions to reduce parasitic capacitance. Additionally, GAA FETs generally require that the GAA gate metal is formed in a narrow vertical region between the bottom of an overlying channel region and the top of an underlying channel region to reduce parasitic capacitance. However, forming the GAA gate metal in a narrow vertical region between the channel regions makes it difficult to achieve the desired threshold voltage (Vt).
Additionally, future technologies have contemplated forming circuits from partial GAA NW FETs (also referred to as partial gate-all-around field effect transistors or partial GAA FETs) to reduce short-channel effects. In a conventional CMOS system on chip (SoC) including a series of partial GAA NW FETs, all of the partial GAA NW FETs of the same type have the same length dielectric separation region. That is, in conventional CMOS SoCs, partial GAA NW FETs having different threshold voltage values (e.g., high voltage threshold (HVT), regular voltage threshold (RVT), low voltage threshold (LVT), and super low voltage threshold (SLVT) FETs) all have dielectric separation regions of the same length. Accordingly, these conventional CMOS SoCs including a series of partial GAA NW FETs are not optimized to achieve the highest performance at lowest dynamic power, compatible with cost.